In conventional photolithographic processing, integrated circuits are manufactured by exposing a pattern of features that are contained on a mask or reticle onto a wafer. Light passing through the transparent portions of the mask activates light sensitive resist materials on the wafer that are then chemically and mechanically processed to create the circuit features. The process continues building up the integrated circuit, layer by layer.
As circuit features become increasingly small and more densely packed, optical and other process distortions occur such that the pattern of features on the mask does not correspond to how the features will print on the wafer. Therefore, numerous resolution enhancement techniques (RETs) have been developed to improve the ability of the mask to print a desired pattern on the wafer. One resolution enhancement technique is optical and process correction (OPC). OPC operates by changing the mask pattern to pre-compensate for expected optical and process distortions such that a pattern of features printed on a wafer will match a desired target layout pattern. Another resolution enhancement technique is the use of subresolution assist features (SRAFs). Such features are small features placed on a mask or reticle that operate to improve how an adjacent mask feature prints.
It is typically desirable to use an SRAF design strategy that is “as aggressive as possible” improve the imaging quality during photolithography, and further to improve the pattern transfer immunity against photolithography process variations. FIG. 3 illustrates the process window precision of a via printed using fewer/smaller SRAFs (side (a)) as compared to the same via printed using more/larger SRAFs (side (b)). As shown, the process window precision is improved by about 30%. It is further typically desirable to prevent SRAFs from printing. This is because, for some designs, a printing SRAF can be a defect that contributes to random defect generation (especially when a printing SRAF forms a resist line). Multiple stacked printing SRAFs in integrated levels can form an actual electrical path to signals that can alter (and even destroy) the circuit behavior. For example, an SRAF printing might cause unintended electrical paths that can ruin the circuit, as shown in FIG. 4. Thus, the designer of a photomask faces the competing goals of increasing the size and density of SRAFs, while at the same time ensuring that no SRAFs print in such as manner as to result in an unintended electrical path.
Accordingly, it is desirable to provide new techniques and methods for designing photomasks with sub-resolution assist features. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.